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INTEGRATED CIRCUITS
DATA SHEET
74LVC1G80 Single D-type flip-flop; positive-edge trigger
Product specification Supersedes data of 2004 Jun 29 2004 Sep 10
Philips Semiconductors
Product specification
Single D-type flip-flop; positive-edge trigger
FEATURES * Wide supply voltage range from 1.65 V to 5.5 V * High noise immunity * Complies with JEDEC standard: - JESD8-7 (1.65 V to 1.95 V) - JESD8-5 (2.3 V to 2.7 V) - JESD8B/JESD36 (2.7 V to 3.6 V). * 24 mA output drive (VCC = 3.0 V) * ESD protection: - HBM EIA/JESD22-A114-B exceeds 2000 V - MM EIA/JESD22-A115-A exceeds 200 V. * CMOS low power consumption * Latch-up performance exceeds 250 mA * Direct interface with TTL levels * Inputs accept voltages up to 5 V * Multiple package options * Specified from -40 C to +85 C and -40 C to +125 C. QUICK REFERENCE DATA GND = 0 V; Tamb = 25 C; tr = tf 2.5 ns. SYMBOL tPHL/tPLH PARAMETER propagation delay CP to Q CONDITIONS VCC = 1.8 V; CL = 30 pF; RL = 1 k VCC = 2.5 V; CL = 30 pF; RL = 500 VCC = 2.7 V; CL = 50 pF; RL = 500 VCC = 3.3 V; CL = 50 pF; RL = 500 VCC = 5.0 V; CL = 50 pF; RL = 500 fmax CI CPD Notes 1. CPD is used to determine the dynamic power dissipation (PD in W). PD = CPD x VCC2 x fi x N + (CL x VCC2 x fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in Volts; N = total load switching outputs; (CL x VCC2 x fo) = sum of the outputs. 2. The condition is VI = GND to VCC. maximum frequency input capacitance power dissipation capacitance per buffer VCC = 3.3 V; notes 1 and 2 VCC = 3.3 V; CL = 50 pF; RL = 500 DESCRIPTION
74LVC1G80
The 74LVC1G80 is a high-performance, low-power, low-voltage, Si-gate CMOS device, superior to most advanced CMOS compatible TTL families. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of this device in a mixed 3.3 V and 5 V environment. This device is fully specified for partial power-down applications using Ioff. The Ioff circuitry disables the output, preventing the damaging backflow current through the device when it is powered down. The 74LVC1G80 provides a single positive-edge triggered D-type flip-flop. Information on the data input is transferred to the Q output pin on the LOW-to-HIGH transition of the clock pulse. The input pin D must be stable one set-up time prior to the LOW-to-HIGH clock transition for predictable operation.
TYPICAL 3.4 2.3 2.5 2.4 1.8 350 5.0 17
UNIT ns ns ns ns ns MHz pF pF
2004 Sep 10
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Philips Semiconductors
Product specification
Single D-type flip-flop; positive-edge trigger
FUNCTION TABLE See note 1. INPUT CP L Note 1. H = HIGH voltage level; L = LOW voltage level; = LOW-to-HIGH CP transition; X = don't care; D L H X
74LVC1G80
OUTPUT Q H L q
q = lower case letter indicates the state of referenced input, one set-up time prior to the LOW-to-HIGH CP transition. ORDERING INFORMATION PACKAGE TYPE NUMBER 74LVC1G80GW 74LVC1G80GV 74LVC1G80GM PINNING PIN TSSOP5; SC-74A 1 2 3 4 5 PIN XSON6 1 2 3 4 5 6 SYMBOL D CP GND Q n.c. VCC input D clock pulse input CP ground (0 V) output Q not connected supply voltage DESCRIPTION TEMPERATURE RANGE -40 C to +125 C -40 C to +125 C -40 C to +125 C PINS 5 5 6 PACKAGE SC-88A SC-74A XSON6 MATERIAL plastic plastic plastic CODE SOT353-1 SOT753 SOT886 MARKING VT V80 VT
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Philips Semiconductors
Product specification
Single D-type flip-flop; positive-edge trigger
74LVC1G80
80
D 1 6 VCC
D CP
1 2
5
VCC
80
4
001aab662
CP
2
5
n.c.
GND
3
Q
GND
3
4
Q
001aab663
Transparent top view
Fig.1 Pin configuration TSSOP5 and SC-74A.
Fig.2 Pin configuration XSON6.
handbook, halfpage handbook, halfpage
1
D
Q
4
1 2
4
2
CP
MNA649
MNA650
Fig.3 Logic symbol.
Fig.4 IEE/IEC logic symbol.
2004 Sep 10
4
Philips Semiconductors
Product specification
Single D-type flip-flop; positive-edge trigger
74LVC1G80
handbook, full pagewidth
CP
C C C C
D
TG C
TG C
Q
MNA651
C
C
TG
TG
C
C
Fig.5 Logic diagram.
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5
Philips Semiconductors
Product specification
Single D-type flip-flop; positive-edge trigger
RECOMMENDED OPERATING CONDITIONS SYMBOL VCC VI VO Tamb tr, tf PARAMETER supply voltage input voltage output voltage operating ambient temperature input rise and fall times VCC = 1.65 V to 2.7 V VCC = 2.7 V to 5.5 V active mode VCC = 0 V; Power-down mode CONDITIONS 0 0 0 -40 0 0 MIN. 1.65
74LVC1G80
MAX. 5.5 5.5 VCC 5.5 +125 20 10 V V V V
UNIT
C ns/V ns/V
LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 60134); voltages are referenced to GND (ground = 0 V). SYMBOL VCC IIK VI IOK VO IO ICC, IGND Tstg Ptot Note 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. PARAMETER supply voltage input diode current input voltage output diode current output voltage output source or sink current VCC or GND current storage temperature power dissipation Tamb = -40 C to +125 C VI < 0 V note 1 VO > VCC or VO < 0 V active mode; note 1 Power-down mode; note 1 VO = 0 V to VCC CONDITIONS - -0.5 - -0.5 -0.5 - - -65 - MIN. -0.5 MAX. +6.5 -50 +6.5 50 +6.5 50 100 +150 250 V mA V mA V mA mA C mW UNIT
VCC + 0.5 V
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Philips Semiconductors
Product specification
Single D-type flip-flop; positive-edge trigger
DC CHARACTERISTICS At recommended operating conditions; voltages are referenced to GND (ground = 0 V). TEST CONDITIONS SYMBOL PARAMETER OTHER Tamb = -40 C to +85 C; note 1 VIH HIGH-level input voltage 1.65 to 1.95 2.3 to 2.7 2.7 to 3.6 4.5 to 5.5 VIL LOW-level input voltage 1.65 to 1.95 2.3 to 2.7 2.7 to 3.6 4.5 to 5.5 VOL LOW-level output voltage VI = VIH or VIL IO = 100 A IO = 4 mA IO = 8 mA IO = 12 mA IO = 24 mA IO = 32 mA VOH HIGH-level output voltage VI = VIH or VIL IO = -100 A IO = -4 mA IO = -8 mA IO = -12 mA IO = -24 mA IO = -32 mA ILI Ioff ICC ICC input leakage current power OFF leakage current quiescent supply current additional quiescent supply current per input pin VI = 5.5 V or GND VI or VO = 5.5 V VI = VCC or GND; IO = 0 A VI = VCC - 0.6 V; IO = 0 A 1.65 to 5.5 1.65 2.3 2.7 3.0 4.5 5.5 0 5.5 2.3 to 5.5 VCC - 0.1 1.2 1.9 2.2 2.3 3.8 - - - - - - - - - - 0.1 0.1 0.1 5 1.65 to 5.5 1.65 2.3 2.7 3.0 4.5 - - - - - - - - - - - - 0.65 x VCC - 1.7 2.0 0.7 x VCC - - - - - - - - - - - VCC (V) MIN. TYP.
74LVC1G80
MAX.
UNIT
- - - - 0.7 0.8 0.3 x VCC 0.1 0.45 0.3 0.4 0.55 0.55 - - - - - - 5 10 10 500
V V V V V V V V V V V V V V V V V V V A A A A
0.35 x VCC V
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7
Philips Semiconductors
Product specification
Single D-type flip-flop; positive-edge trigger
74LVC1G80
TEST CONDITIONS SYMBOL PARAMETER OTHER Tamb = -40 C to +125 C VIH HIGH-level input voltage 1.65 to 1.95 2.3 to 2.7 2.7 to 3.6 4.5 to 5.5 VIL LOW-level input voltage 1.65 to 1.95 2.3 to 2.7 2.7 to 3.6 4.5 to 5.5 VOL LOW-level output voltage VI = VIH or VIL IO = 100 A IO = 4 mA IO = 8 mA IO = 12 mA IO = 24 mA IO = 32 mA VOH HIGH-level output voltage VI = VIH or VIL IO = -100 A IO = -4 mA IO = -8 mA IO = -12 mA IO = -24 mA IO = -32 mA ILI Ioff ICC ICC input leakage current power OFF leakage current quiescent supply current additional quiescent supply current per input pin VI = 5.5 V or GND VI or VO = 5.5 V VI = VCC or GND; IO = 0 A VI = VCC - 0.6 V; IO = 0 A 1.65 to 5.5 1.65 2.3 2.7 3.0 4.5 5.5 0 5.5 2.3 to 5.5 VCC - 0.1 0.95 1.7 1.9 2.0 3.4 - - - - - - - - - - - - - - - - - - - - 100 200 200 5000 V V V V V V A A A A 1.65 to 5.5 1.65 2.3 2.7 3.0 4.5 - - - - - - - - - - - - 0.1 0.7 0.45 0.60 0.80 0.80 V V V V V V 0.65 x VCC - 1.7 2.0 0.7 x VCC - - - - - - - - - - - - - - - 0.7 0.8 0.3 x VCC V V V V V V V VCC (V) MIN. TYP. MAX. UNIT
0.35 x VCC V
Note 1. All typical values are measured at VCC = 3.3 V and Tamb = 25 C.
2004 Sep 10
8
Philips Semiconductors
Product specification
Single D-type flip-flop; positive-edge trigger
AC CHARACTERISTICS GND = 0 V. TEST CONDITIONS SYMBOL PARAMETER WAVEFORMS Tamb = -40 C to +85 C; note 1 tPHL/tPLH propagation delay CP to Q see Figs 6 and 8 1.65 to 1.95 2.3 to 2.7 2.7 3.0 to 3.6 4.5 to 5.5 tsu set-up time D to CP see Figs 7 and 8 1.65 to 1.95 2.3 to 2.7 2.7 3.0 to 3.6 4.5 to 5.5 th hold time D to CP see Figs 7 and 8 1.65 to 1.95 2.3 to 2.7 2.7 3.0 to 3.6 4.5 to 5.5 tW clock pulse with HIGH or LOW see Figs 7 and 8 1.65 to 1.95 2.3 to 2.7 2.7 3.0 to 3.6 4.5 to 5.5 fmax maximum clock pulse frequency see Figs 7 and 8 1.65 to 1.95 2.3 to 2.7 2.7 3.0 to 3.6 4.5 to 5.5 1.0 0.5 0.5 0.9 0.5 2.3 1.5 1.5 1.3 1.1 0 0 +0.5 0.9 +0.5 3.0 2.5 2.5 2.5 2.0 160 160 160 160 200 3.4 2.3 2.5 2.4 1.8 0.8 0.6 0.5 0.4 0.5 -0.6 -0.4 -0.2 0.2 -0.1 1.1 0.7 0.6 0.6 0.5 300 350 350 350 400 VCC (V) MIN. TYP.
74LVC1G80
MAX.
UNIT
9.9 7.0 6.0 5.0 4.5 - - - - - - - - - - - - - - - - - - - -
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns MHz MHz MHz MHz MHz
2004 Sep 10
9
Philips Semiconductors
Product specification
Single D-type flip-flop; positive-edge trigger
74LVC1G80
TEST CONDITIONS SYMBOL PARAMETER WAVEFORMS Tamb = -40 C to +125 C tPHL/tPLH propagation delay CP to Q see Figs 6 and 8 1.65 to 1.95 2.3 to 2.7 2.7 3.0 to 3.6 4.5 to 5.5 tsu set-up time D to CP see Figs 7 and 8 1.65 to 1.95 2.3 to 2.7 2.7 3.0 to 3.6 4.5 to 5.5 th hold time D to CP see Figs 7 and 8 1.65 to 1.95 2.3 to 2.7 2.7 3.0 to 3.6 4.5 to 5.5 tW clock pulse with HIGH or LOW see Figs 7 and 8 1.65 to 1.95 2.3 to 2.7 2.7 3.0 to 3.6 4.5 to 5.5 fmax maximum clock pulse frequency see Figs 7 and 8 1.65 to 1.95 2.3 to 2.7 2.7 3.0 to 3.6 4.5 to 5.5 Note 1. All typical values are measured at Tamb = 25 C. 1.0 0.5 0.5 0.9 0.5 2.3 1.5 1.5 1.3 1.1 0 0 0.5 0.9 0.5 3.0 2.5 2.5 2.5 2.0 160 160 160 160 200 - - - - - - - - - - - - - - - - - - - - - - - - - 13.0 9.0 8.0 6.5 6.0 - - - - - - - - - - - - - - - - - - - - ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns MHz MHz MHz MHz MHz VCC (V) MIN. TYP. MAX. UNIT
2004 Sep 10
10
Philips Semiconductors
Product specification
Single D-type flip-flop; positive-edge trigger
AC WAVEFORMS
74LVC1G80
handbook, full pagewidth
VI D input GND VI CP input GND t PHL VOH Q output VOL VM VM
MNA652
VM
VM
t PLH
INPUT VCC 1.65 V to 1.95 V 2.3 V to 2.7 V 2.7 V 3.0 V to 3.6 V 4.5 V to 5.5 V VM 0.5 x VCC 0.5 x VCC 1.5 V 1.5 V 0.5 x VCC VCC VCC 2.7 V 2.7 V VCC VI tr = tf 2.0 ns 2.0 ns 2.5 ns 2.5 ns 2.5 ns
VOL and VOH are typical output voltage drop that occur with the output load.
Fig.6 Clock (CP) to output (Q) propagation delay times.
2004 Sep 10
11
Philips Semiconductors
Product specification
Single D-type flip-flop; positive-edge trigger
74LVC1G80
handbook, full pagewidth
VI D input GND th t su 1/fmax VI CP input GND tW t PHL VOH Q output VOL VM
MNA653
VM
th t su
VM
t PLH
INPUT VCC 1.65 V to 1.95 V 2.3 V to 2.7 V 2.7 V 3.0 V to 3.6 V 4.5 V to 5.5 V VM 0.5 x VCC 0.5 x VCC 1.5 V 1.5 V 0.5 x VCC VCC VCC 2.7 V 2.7 V VCC VI tr = tf 2.0 ns 2.0 ns 2.5 ns 2.5 ns 2.5 ns
The shaded areas indicate when the input is permitted to change for predictable output performance. VOL and VOH are typical output voltage drop that occur with the output load.
Fig.7
Clock (CP) to output (Q) propagation delays, clock pulse width, D to CP set-up times, the D to CP hold times and maximum clock pulse frequency.
2004 Sep 10
12
Philips Semiconductors
Product specification
Single D-type flip-flop; positive-edge trigger
74LVC1G80
VEXT VCC PULSE GENERATOR VI D.U.T. RT CL RL VO RL
mna616
VCC 1.65 V to 1.95 V 2.3 V to 2.7 V 2.7 V 3.0 V to 3.6 V 4.5 V to 5.5 V
VI VCC VCC 2.7 V 2.7 V VCC
CL 30 pF 30 pF 50 pF 50 pF 50 pF
RL 1 k 500 500 500 500
VEXT tPLH/tPHL open open open open open tPZH/tPHZ GND GND GND GND GND tPZL/tPLZ 2 x VCC 2 x VCC 6V 6V 2 x VCC
Definitions for test circuit: RL = Load resistor. CL = Load capacitance including jig and probe capacitance. RT = Termination resistance should be equal to the output impedance Zo of the pulse generator.
Fig.8 Load circuitry for switching times.
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Philips Semiconductors
Product specification
Single D-type flip-flop; positive-edge trigger
PACKAGE OUTLINES
TSSOP5: plastic thin shrink small outline package; 5 leads; body width 1.25 mm
74LVC1G80
SOT353-1
D
E
A X
c y HE vMA
Z
5
4
A2 A1 (A3) A
1
e e1 bp
3
wM detail X
Lp L
0
1.5 scale
3 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A max. 1.1 A1 0.1 0 A2 1.0 0.8 A3 0.15 bp 0.30 0.15 c 0.25 0.08 D(1) 2.25 1.85 E(1) 1.35 1.15 e 0.65 e1 1.3 HE 2.25 2.0 L 0.425 Lp 0.46 0.21 v 0.3 w 0.1 y 0.1 Z(1) 0.60 0.15 7 0
Note 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. OUTLINE VERSION SOT353-1 REFERENCES IEC JEDEC MO-203 JEITA SC-88A EUROPEAN PROJECTION ISSUE DATE 00-09-01 03-02-19
2004 Sep 10
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Philips Semiconductors
Product specification
Single D-type flip-flop; positive-edge trigger
74LVC1G80
Plastic surface mounted package; 5 leads
SOT753
D
B
E
A
X
y
HE
vMA
5
4
Q
A A1 c
1
2
3
detail X
Lp
e
bp
wM B
0
1 scale
2 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A 1.1 0.9 A1 0.100 0.013 bp 0.40 0.25 c 0.26 0.10 D 3.1 2.7 E 1.7 1.3 e 0.95 HE 3.0 2.5 Lp 0.6 0.2 Q 0.33 0.23 v 0.2 w 0.2 y 0.1
OUTLINE VERSION SOT753
REFERENCES IEC JEDEC JEITA SC-74A
EUROPEAN PROJECTION
ISSUE DATE 02-04-16
2004 Sep 10
15
Philips Semiconductors
Product specification
Single D-type flip-flop; positive-edge trigger
74LVC1G80
XSON6: plastic extremely thin small outline package; no leads; 6 terminals; body 1 x 1.45 x 0.5 mm
SOT886
b 1 2 3 4x L1 L
(2)
e
6 e1
5 e1
4
6x
(2)
A
A1 D
E
terminal 1 index area 0 DIMENSIONS (mm are the original dimensions) UNIT mm A (1) max 0.5 A1 max 0.04 b 0.25 0.17 D 1.5 1.4 E 1.05 0.95 e 0.6 e1 0.5 L 0.35 0.27 L1 0.40 0.32 1 scale 2 mm
Notes 1. Including plating thickness. 2. Can be visible in some manufacturing processes. OUTLINE VERSION SOT886 REFERENCES IEC JEDEC MO-252 JEITA EUROPEAN PROJECTION ISSUE DATE 04-07-15 04-07-22
2004 Sep 10
16
Philips Semiconductors
Product specification
Single D-type flip-flop; positive-edge trigger
DATA SHEET STATUS LEVEL I DATA SHEET STATUS(1) Objective data PRODUCT STATUS(2)(3) Development DEFINITION
74LVC1G80
This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN).
II
Preliminary data Qualification
III
Product data
Production
Notes 1. Please consult the most recently issued data sheet before initiating or completing a design. 2. The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. 3. For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status. DEFINITIONS Short-form specification The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. DISCLAIMERS Life support applications These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes Philips Semiconductors reserves the right to make changes in the products including circuits, standard cells, and/or software described or contained herein in order to improve design and/or performance. When the product is in full production (status `Production'), relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified.
2004 Sep 10
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Philips Semiconductors - a worldwide company
Contact information For additional information please visit http://www.semiconductors.philips.com. Fax: +31 40 27 24825 For sales offices addresses send e-mail to: sales.addresses@www.semiconductors.philips.com.
(c) Koninklijke Philips Electronics N.V. 2004
SCA76
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
R20/06/pp18
Date of release: 2004
Sep 10
Document order number:
9397 750 13767

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